Technique for producing small islands of silicon on insulator

ABSTRACT

Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defmed on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

FIELD OF THE INVENTION

[0001] The present invention relates to methods and apparatus forisolating semiconductor devices with silicon on insulator technology,and in particular, for forming isolated silicon islands using sub-microntechnology.

BACKGROUND OF THE INVENTION

[0002] The advantages of silicon on insulator (SOI) technology forcomplementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs)are well documented. In general, undesired p-n junction capacitancebetween a source/drain and a substrate is reduced by approximatelytwenty-five-percent when using SOI technology. Furthermore, activecurrent consumption is less and device access time is equivalent to thatof similar devices formed on bulk-silicon substrates. Other advantagesof SOI technology include suppression of the short channel effect,suppression of the body-effect, high punch-through immunity, and freedomfrom latch-up and soft errors. As the demand increases forbattery-operated equipment, SOI technology is becoming increasingly morepopular due to its low power requirements and high speeds.

[0003] There are many different techniques for isolating devices in ICs.A technique is selected according to its different attributes, such as:minimum isolation spacing, surface planarity, process complexity, anddensity of defects generated during fabrication.

[0004] SIMOX (Separation by IMplanted OXygen) technology is one methodfor forming SOI structures. SIMOX entails implanting a high dose ofoxygen ions at a sufficiently deep level within a silicon substrate. Asubsequent anneal step forms a buried oxide layer in the substrate.After the anneal step, an additional layer of epitaxial silicon isusually deposited to obtain a sufficiently thick silicon layer on whichto form a device. Disadvantages of using SIMOX include its high expenseand yield loss, which undesirably decreases achievable chip density.

[0005] Another technique for forming an isolation layer in a substrateis by the wafer bonding method. Using this technique, two oxidizedsilicon wafers are fused together through a high-temperature furnacestep. However, this technique increases the substrate thickness, whichis often a critical dimension. Furthermore, wafer bonding techniques areoften plagued by low production yield due to particles/voids, whichprevent adequate bonding between the two wafers in such areas.

[0006] Another technique used for forming an isolation layer in asubstrate is by forming silicon islands through a series of etch andoxidation steps. For example, U.S. Pat. No. 4,604,162 (hereinafter the'162 patent) uses a series of a pad oxide layer, a silicon nitridelayer, and a silicon dioxide layer, which is photolithographicallymasked and anisotropically etched to define silicon islands capped witha silicon nitride layer. Then, a second anisotropic etch (such as areactive ion etch (RIE)) removes further substrate material between thesilicon islands. The depth of the second anisotropic etch isproportional to the width of the silicon islands. A subsequent oxidationstep forms silicon dioxide, undercutting the silicon islands andisolating each of them from surrounding regions. However, this techniquehas not been used commercially because it is too costly and consumes toomuch time to oxidize an area having an effective width as great as thatof the feature size. Another disadvantage of this technique is that theresulting isolated silicon structure has excess mechanical stress andcrystal damage at each of its corners, due to oxidation around theentirety of each individual island, which is necessary for its completeisolation. Furthermore, the method described in the patent applicationrequires an additional planarization step, which adds complexity to thefabrication process.

[0007] There is a need for an effective isolation technique forsub-micron semiconductor technology that is efficient and simple. Aprimary concern in the fabrication of ICs is simplicity and minimizationof process steps. There is a need for an isolation technique that isinexpensive and compatible with large volume CMOS manufacturingtechnology. Furthermore, an isolation technique, which allowsfabrication of highly dense ICs without increasing the dimensions of theIC is needed.

SUMMARY OF THE INVENTION

[0008] Silicon on insulator (SOI) rows and islands are formed forsubsequent sub-micron device formation. For example, complementarymetal-oxide-semiconductor (CMOS) transistors are later formed on suchSOI rows, isolated from each other using standard techniques, such asLOCal Oxidation of Silicon (LOCOS). To form the rows, trenches aredirectionally-etched in a silicon substrate, leaving rows of siliconbetween the trenches.

[0009] Silicon nitride is then deposited over the trenches, extendingpartly down the sides of the trenches. An isotropic chemical etch isthen used to partially undercut narrow rows of silicon in the substrate.It is important to use an isotropic etch for this step to compensate forthe volume of oxide to be formed. In general, the volume of oxide formedis approximately twice that of the silicon consumed. Furthermore, anisotropic etch is necessary to advantageously minimize the subsequentoxidation time needed to fully undercut the silicon rows. The subsequentoxidation step fully undercuts the rows of silicon, isolating thesilicon rows from adjacent active areas.

[0010] One advantage of this invention is that by using narrow,sub-micron rows of silicon and appropriately designed processconditions, generally planar structures are formed in an integratedcircuit (IC). The larger volume of oxide fills the trenches between therows. This avoids complex and expensive planarization techniques, suchas employed in older micron dimension technologies. Furthermore, suchoxidation minimizes mechanical stress and crystal damage in resultingstructures, when used to finish undercutting rows, as compared toundercutting individual silicon islands.

[0011] This invention enables formation of sub-micron devices, such asCMOS transistors, having a high chip density, without increasing thedimensions of the IC. This method yields isolated active regions, havinga high degree of regularity and yield, formed in an inexpensive manner.This method is compatible with CMOS IC manufacturing technology due toits simplicity and minimal number of process steps. Regular arraystructures, such as dynamic random access memories (DRAMs) particularlybenefit from this invention, separated on the silicon rows using LOCOStechnology.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIGS. 1A to 1D are cross-sectional representations of a method forforming isolated silicon rows.

[0013]FIG. 1E is a plan view of isolated silicon islands formed on theisolated silicon rows shown in FIG. 1D.

[0014]FIG. 1F is a cross-sectional representation of NMOS and PMOStransistors formed on the isolated silicon islands shown in FIG. 1E.

[0015]FIG. 1G is a plan view of the NMOS and PMOS transistors shown inFIG. 1F.

DESCRIPTION OF THE EMBODIMENTS

[0016] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined by the appendedclaims. Numbering in the Figures is usually done with the hundreds andthousands digits corresponding to the figure number, with the exceptionthat the same components may appear in multiple figures.

[0017] As shown in FIG. 1A, a silicon substrate 101 isdirectionally-etched to form trenches 102, leaving rows 104 of siliconprotruding from the substrate 101. The silicon rows 104 have widths ofone micron or less. The trench 102 depth and width are approximatelyequal to the width of the silicon rows 104. The direction of the etchvaries with the crystal orientation of the substrate 101. In oneembodiment, the etch direction is orthogonal to the plane of thesubstrate 101. For complementary metal-oxide-semiconductor (CMOS)devices, substrates 101 having a {100} crystallographic orientation arecommonly used due to the ability to achieve small surface statedensities on such substrates. Therefore, the direction of the etch ispreferably in the <100> direction. To form the trenches, the substrate101 is oxidized at a temperature of approximately 900 to 1,100 degreesCelsius, covered with silicon nitride (Si₃N₄), masked and etched to formexposed oxide regions using standard techniques. Then, the exposed oxideregions are etched away with a directional etchant, preferably areactive ion etch (RIE), forming trenches 102 in the substrate 101.

[0018] Next, as shown in FIG. 1B, a Si₃N₄ cap 106 is formed on thesilicon rows 104. The Si₃N₄ 106 is deposited over the structure, usingtechniques well known in the art, such as chemical vapor deposition(CVD). Si₃N₄ 106 forms on the tops of the silicon rows 104 and partlydown the sides of the trenches 102. Material overhang at the top of thetrench 102 prevents Si₃N₄ 106 from covering the lower sides of thetrenches 102. However, some Si₃N₄ 106 is deposited onto the bottom ofthe trenches 102.

[0019] A photoresist mask is used to cover the silicon rows 104 and anetch is then used to remove residual Si₃N₄ 106 on the bottom of thetrenches 102 and then an isotropic chemical etch is used to partiallyundercut the rows 104 of silicon, as shown in FIG. 1C. A standardchemical etch using hydrofluoric acid (HF) or a commercial etchant soldunder the trade name CP4 (a mixture of approximately 1 part (46% HF): 1part (CH₂COOH):3 parts (HNO₂)) is used for the isotropic etchant. It isimportant to use an isotropic etch for this step to compensate for thevolume of oxide to be formed in the next step. In general, the volume ofoxide formed is approximately twice that of the silicon 101 consumed.Partially undercutting the silicon rows 104, reduces the effective widthof the rows 104 to a distance 110 small enough that a relatively short,simple oxidation can fully undercut the silicon rows 104. Fullyundercutting the rows 104 of silicon is possible because the width 108of the rows 104 is one micron or less.

[0020] The substrate 101 is then oxidized using a standard siliconprocessing furnace at a temperature of approximately 900 to 1,100degrees Celsius, as shown in FIG.1D. A wet, oxidizing ambient is used inthe furnace chamber to oxidize the exposed silicon regions on the lowerpart of the trenches 102 in a parallel direction to the surface of thesubstrate 101. The substrate 101 is oxidized for a time period, suchthat oxide 112 fully undercuts the bottom of the silicon rows 104,leaving isolated silicon rows 104. By using narrow, sub-micron rows 104of silicon and appropriately designed process conditions, generallyplanar structures are formed. The larger volume of oxide fills thetrenches 102 between the rows 104. This avoids the need for complex andexpensive planarization techniques, such as employed in older microndimension technologies. The time period for oxidation depends on thewidth 108 of the rows 104 and the effective width 110 after the partialundercut step. As the desired size of the silicon rows 104 decreases, sodoes the required oxidation time. For example, for sub-microntechnology, oxidation time is approximately 3 to 4 hours. For sub-0.25micron technology, oxidation time is approximately 1 hour.

[0021] Active areas 114 are then defined on the individual silicon rows104, using a standard process, such as LOCal Oxidation of Silicon(LOCOS), as shown in FIG. 1E, to form oxide 116 between the active areas114. Depending on the width of the silicon rows 104, the area of theseactive areas 114 is approximately one square micron or less forsub-micron technology and approximately 0.0625 square microns or lessfor sub-0.25 micron technology. The resulting isolated active areas 114are not subjected to as much mechanical stress and crystal damage as areactive areas formed by prior art techniques of oxidizing to undercuteach individual active area, which are excessively stressed and damagedat each corner of the active area.

[0022] Devices are then formed on the resulting silicon islands 114, asshown in FIGS. 1F and 1G, according to methods well known in the art.For example, when forming CMOS transistors, a gate oxide layer 118,source/drain regions 120, 122, and a gate 124 are formed for eachtransistor on an individual silicon island 114. For PMOS transistors,source/drain regions 120 are doped to form (p+) regions. For NMOStransistors, source/drain regions 122 are doped to form (n+) regions.Further standard process techniques are then used to connect the devicesto form circuits, such as dynamic random access memory (DRAM) devices.

[0023] The process described above is a low cost, simple method forforming sub-micron SOI devices. The method is compatible with existinglarge volume manufacturing conditions. Resulting devices are able toformed on semiconductor chips in a highly dense, arrayed manner. Thus,the invention enables formation of very high density and very highperformance CMOS integrated circuits, DRAMs, as well as other integratedcircuits.

[0024] It should be noted that in CMOS technology, many times certainareas of the semiconductor die described as having a particular doping,could quite easily be of a different doping, promoting a different typeof charge carrier. In such instances, if one were to reverse the primarycarriers in all areas of the die and adjust for carrier mobility, theinvention would operate in the same manner as described herein withoutdeparting from the scope and spirit of the present invention.

[0025] It is to be understood that the above description is intended tobe illustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reviewing the abovedescription. The scope of the invention should, therefore, be determinedwith reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

What is claimed is:
 1. A method for manufacturing a silicon on insulator substrate, comprising the steps of: directionally etching a silicon substrate, to form a plurality of trenches between protruding silicon rows; forming a silicon nitride cap on the silicon rows, extending partway down the sides of the trenches; isotropically etching the trenches, to partially undercut the silicon rows; and oxidizing the substrate, to fully undercut the silicon rows.
 2. The method of claim 1, wherein the silicon substrate has a {100} crystallographic orientation and the directional etch is in the <100> direction.
 3. The method of claim 1, wherein the directional etchant comprises a reactive ion etch.
 4. The method of claim 1, wherein the isotropic etchant comprises hydrofluoric acid.
 5. The method of claim 1, wherein the silicon rows have a width dimension of one micron or less.
 6. The method of claim 1, wherein the silicon rows have a width dimension of 0.25 microns or less.
 7. The method of claim 1, wherein the directional etch is approximately as deep as the width of the silicon rows and approximately as wide as the width of the silicon rows.
 8. The method of claim 1, wherein the oxidizing step comprises oxidizing the substrate in a wet oxidizing ambient at a temperature of approximately 900 to 1,100 degrees Celsius.
 9. The method of claim 1, and further comprising the step of: defining a plurality of active areas on the silicon rows by local oxidation of silicon.
 10. The method of claim 9, and further comprising the step of: forming a transistor on each of a plurality of the active areas.
 11. A silicon on insulator structure, comprising: a plurality of silicon rows, having a width dimension of one micron or less, embedded in an oxidized substrate; and a plurality of oxide rows between the silicon rows.
 12. The structure of claim 11, wherein the oxide rows have a width dimension of one micron or less.
 13. The structure of claim 11, wherein the silicon rows have a width dimension of 0.25 microns or less.
 14. The structure of claim 11, wherein the oxide rows have a width dimension of 0.25 microns or less.
 15. A plurality of active areas on a semiconductor substrate, comprising: a plurality of isolated silicon active areas, having an area of one square micron or less, embedded in an oxidized substrate; and a plurality of oxide rows between the silicon active areas in one direction.
 16. The structure of claim 15, and further comprising: a plurality of transistors formed on each of a plurality of the silicon active areas.
 17. The structure of claim 15, wherein the oxide rows have a width dimension of one micron or less.
 18. The structure of claim 15, wherein the oxide rows have a width dimension of 0.25 microns or less.
 19. The structure of claim 15, wherein the area of the silicon active areas is 0.0625 square microns or less.
 20. The structure of claim 15, wherein the active areas are isolated using local oxidation of silicon. 